Silicon on insulator structures (“SOI structures”) generally include a handle wafer, a silicon layer (also characterized as a “device layer”), and a dielectric layer (such as an oxide layer) between the handle wafer and the silicon layer. Many silicon semiconductor device designs benefit from using an SOI substrate rather than a bulk silicon polished wafer or epitaxial layer coated substrate. Applications in high volume manufacturing typically benefit from the improved isolation of the device layer, enabling high bandwidth transistors with reduced electro-magnetic cross-talk between adjacent cells within a device.
SOI structures may be prepared from silicon wafers sliced from single crystal silicon ingots grown in accordance with the Czochralski (Cz) method. In one method for preparing an SOI substrate, a dielectric layer is deposited on a polished front surface of a donor wafer. Ions are implanted at a specified depth beneath the front surface of the donor wafer to form a damage layer in the donor wafer at the specified implant depth. The front surface of the donor wafer is then bonded to a handle wafer and the two wafers are pressed to form a bonded wafer pair. The bonded wafer pair is then cleaved along a cleave plane within the damage layer to remove the portion of the donor wafer below the damage layer, leaving behind a thin silicon layer (i.e., the device layer) atop the handle wafer to form the SOI layered substrate.
The mechanical cleave of the bonded wafer pair may result in non-uniform device layer thickness as the cleave progresses from the leading edge at which the cleave commences toward the trailing edge at which the bonded wafers fully separate. Further, in some instances, the cleave may fail and the bonded wafer structure is not cleaved along the desired cleave plane or the bonded wafer structure does not cleave at all. Variations in the cleave are conventionally monitored by operator observation at a downstream process, which may not provide timely feedback to monitor or adjust the appropriate process upstream or at cleaving.
There is a need for cleave systems and methods for separating bonded wafer structures that provide relatively quick feedback relating to the quality of the cleaving process and/or that allow the cleave process to be tuned for subsequent cleaves. There is also a need for cleave monitoring systems that are mountable to existing cleaving apparatus to allow the cleave process to be better monitored.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.